Sequencing & Clock

Clk Div/Mult

Clock divider and multiplier - turn one master tempo into many related ones, slower OR faster.

What is a Clk Div/Mult?

A clock divider takes one incoming clock signal and produces several new clocks at related but different speeds. Divide by 2 fires every other input pulse. Divide by 4 fires every fourth. Multiply by 3 fires three times for every input pulse. The math is integer arithmetic; the result is a family of tempos all locked to one master grid.

This sounds like a small thing and is in fact the secret architecture trick behind almost every polyrhythmic modular patch ever made. A single master clock going 120 BPM becomes, through a divider, a kick on /4, a snare on /2, hi-hats on /1 (pass-through), and a slow filter sweep on /16 — four parts moving at different rates that nonetheless line up on the downbeat because they all started from the same source.

Internally, division is the easy part: count input rising edges and fire every Nth one. There is zero added jitter because the output is exactly the input timing, just thinned. Multiplication is harder — the module has to predict the future. It measures the period between recent input edges, then runs an internal phase-locked sub-oscillator at N times that rate, hard-resyncing on every new input edge to prevent drift. The first measurement requires at least two input edges, so a freshly patched multiplier needs a moment to lock.

Our Clk Div/Mult

Our Clk Div is 8 HP with four independent outputs, each selectable from /16 (sixteen times slower) through x16 (sixteen times faster), with unity (/1, pass-through) at the center. That is 31 ratios per output, all chosen with one knob.

Divisions are bit-exact: we count input rising edges and fire every Nth one with no added jitter. Multiplications use a period-measuring phase-locked sub-oscillator per output — we measure the time between the last two input edges, run a sub-phase accumulator at N times that rate, and hard-resync on every input edge so the multiplied gates stay locked even if the master clock slowly drifts.

Patch a Clock's main and reset outputs into our CLK and RST inputs and you have a four-way polyrhythmic engine in 14 HP combined. The PW knob controls gate width across all four outputs simultaneously, so you can dial short staccato triggers or long sustained gates in one move.

In a patch

A divider sits between a clock and the modules that need different tempos from it. The canonical drum-machine wiring: master clock → divider → kick on /4, snare on /2, hi-hat on /1, percussion on x2. The same idea drives a melodic sequencer at half-time while a separate sequencer for accent gates runs at full speed.

For pattern-based rhythm rather than ratio-based rhythm, reach for a Euclidean generator instead — Euclidean answers a different question (how do I distribute K hits across N steps evenly?), while a divider answers how do I make this clock go N times slower or faster?. Both can be on the same patch and they compose well: one clock divides into four feeds, three of those feeds drive Euclidean channels.

Inputs

CLK (gate) — Clock input. The incoming gate signal to divide or multiply. Each rising edge is counted.
RST (gate) — Reset input. Clears all counters and phases on a rising edge. Use to resync divisions with other modules.

Outputs

OUT 1 (gate) — Output 1 gate. Speed set by Ratio 1 knob. Default: /2 (half speed).
OUT 2 (gate) — Output 2 gate. Default: /4 (quarter speed).
OUT 3 (gate) — Output 3 gate. Default: /8 (eighth speed).
OUT 4 (gate) — Output 4 gate. Default: x2 (double speed).

Controls

Ratio 1 — Speed ratio for Output 1. Ranges from /16 (index 0) through /1 (index 15, pass-through) to x16 (index 30). Default: /2 (index 14).
Ratio 2 — Speed ratio for Output 2. Default: /4 (index 12).
Ratio 3 — Speed ratio for Output 3. Default: /8 (index 8).
Ratio 4 — Speed ratio for Output 4. Default: x2 (index 16).
PW — Pulse width for all outputs (0.1 to 0.9). Controls how long each gate stays high.

Inspired by

A classic clock divider AND multiplier topology with four independent outputs spanning /16 through x16. Divisions count input edges with zero added jitter; multiplications use period measurement and a phase-locked sub-oscillator with per-edge resync, a contemporary touch on a canonical utility.

4ms RCD
Make Noise Tempi
classic clock divider topology

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